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Senior Engineer for Synthesis / Automated Test Pattern (f/m/div)
... -end flow Write RTL , perform simulations , linting, synthesis, logic equivalence checks, and automated test pattern generation Collaborate with AMS IP project teams for IP designs and ...heute neu |
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Senior Staff Test Engineer (f/m/div)
... -driven and flexible character who finds problem-solving exciting as readjustments of e.g. test procedures are part of your daily work routine . Furthermore, you possess the ability to ...vor 2 Tagen |
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Senior Test Engineer m/w/d
... Erfahrung mit der Arbeit in agilen Teams und agilen Methoden sowie mit dem Testen verteilter Anwendungen und deren Interaktionen in Microservices-Architekturen Solide Kenntnisse der CI ...vor 1 Woche |
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Senior Power Electronics Engineer Wafer Technology Development (f/m/div)
... process control, process control monitor design/layout, wafer-level reliability test and electrical characterization, failure analysis techniques, TCAD simulations, IP generation ...heute neu |
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Material Scientist as Senior Power Systems Engineer Low Voltage (f/m/div)
... process control, process control monitor design/layout, wafer-level reliability test and electrical characterization, failure analysis techniques, TCAD simulations, IP generation ...heute neu |
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Electrical Engineer as Staff Engineer Low Voltage Technology (f/m/div)
... process control, process control monitor design/layout, wafer-level reliability test and electrical characterization, failure analysis techniques, TCAD simulations, IP generation ...heute neu |
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Senior Staff Engineer - RTL Design (f/m/div)
... -end flow Write RTL , perform simulations , linting, synthesis, logic equivalence checks, and automated test pattern generation Collaborate with AMS IP project teams for IP designs and ...heute neu |
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Lead Principal Engineer SoC Architecture (f/m/div)
... -functional teams in Analog/Digital Design, Verification, Firmware Development, Validation, Test, and Project Management to deliver first-pass functional silicon Influencing roadmaps ...heute neu |
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Senior Staff Engineer - RTL, Logic Equivalence (f/m/div)
... -end flow Write RTL , perform simulations , linting, synthesis, logic equivalence checks, and automated test pattern generation Collaborate with AMS IP project teams for IP designs and ...heute neu |
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Electrical Engineer as Senior Staff Engineer IP Designs (f/m/div)
... -end flow Write RTL , perform simulations , linting, synthesis, logic equivalence checks, and automated test pattern generation Collaborate with AMS IP project teams for IP designs and ...heute neu |
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